//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 09/26/2016 11:10:45 AM
// Design Name: 
// Module Name: key_proc
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps 
module key_proc(
    input wire        clk,
    input wire        rstn,

    input wire        clk_10k,  

    input      [15:0] key_in,
    output reg [15:0] key_out,
    output reg        key_intr
);
//--------------------------------------------------------
reg[15:0]  keyin_ff1;
reg        key_touch;
reg        key_press;
reg[1:0]   state;
reg        intout;
reg[2:0]   intout_ffx;
reg        clr;
reg[15:0]  counter;
//--------------------------------------------------------
always @(posedge clk_10k) keyin_ff1 <= key_in;
always @(posedge clk_10k) key_touch <= (keyin_ff1 == 16'hffff)?1'b0:1'b1;
always @(posedge clk_10k) key_press <= (keyin_ff1[7:0] == 8'hff)?1'b0:1'b1;
//--------------------------------------------------------
always @(posedge clk_10k) begin
    case (state )
        2'b00: begin
            intout <= 0;
            clr    <= 0;
            state  <= (key_touch)? 1:0;
        end
        2'b01: begin
            if (counter == 200) begin
                intout <= key_touch ? 1'b1:1'b0;
                state  <= 2;
                clr    <= 0; 
            end
            else begin
                clr <= 1;
            end
        end
        2'b10: begin
            if (key_press) begin
                if (counter == 10000) begin
                    state  <= 3;
                    intout <= 1;
                    clr    <= 0;
                end
                else begin
                    clr    <= 1;
                    intout <= 0;
                end
            end
            else  begin
                state  <= 0;
                intout <= 0;
                clr    <= 0;
            end
        end
        2'b11: begin
           if (key_press)  begin
                if (counter == 1000) begin
                    intout <= 1;
                    clr    <= 0;
                end
                else  begin
                    clr    <= 1;
                    intout <= 0;
                end
           end
           else begin
                state  <= 0;
                intout <= 0;
                clr    <= 0;
            end
        end
        default: begin
            state  <= 0;
        end
    endcase
end
//--------------------------------------------------------
always @(posedge clk_10k ) counter    <= (clr == 0)?0:(counter +1);
//-------------------------------------------------------- 
always @(posedge clk ) intout_ffx <= {intout_ffx[1:0],intout};
always @(posedge clk ) key_intr   <= (intout_ffx[2:1] == 2'b01) ? 1'b1:1'b0;
always @(posedge clk ) key_out    <= key_in;
//--------------------------------------------------------

endmodule
